The present invention relates to a manufacturing technology of a semiconductor device, in particular to a technology effective in applying it to the manufacture of a semiconductor device having nonvolatile memory cells of a split gate structure.
For example, Japanese Unexamined Patent Publication No. Hei 06 (1994)-151783 (Patent Literature 1): discloses a semiconductor device having a linear dummy pattern formed at a boundary between a memory cell array region and a peripheral circuit region; and describes a structure wherein the gate of a memory cell has a double layer structure comprising polycrystalline Si, the dummy pattern has a single layer structure comprising polycrystalline Si, and the height of the dummy pattern from the principal face of a semiconductor substrate is lower than the height of the gate of the memory cell.